1樓：依依呀呀啊哈
這是我自己寫的，應該能滿足你的要求！
頂層實體
--topo.vhd
----
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity top is
port(
clk1hz :in std_logic;
set :in std_logic;
node :in std_logic;
led1 :out std_logic_vector(6 downto 0);
led2 :out std_logic_vector(6 downto 0);
led3 :out std_logic_vector(6 downto 0);
led4 :out std_logic_vector(6 downto 0);
led5 :out std_logic_vector(6 downto 0);
led6 :out std_logic_vector(6 downto 0)
);end top;
architecture rtl of top is
component adjuster
port(
clk1hz :in std_logic;
set :in std_logic;
node :in std_logic;
en :in std_logic;
s_enout :in std_logic;
m_enout :in std_logic;
clk :out std_logic;
s_ce :out std_logic;
m_ce :out std_logic;
h_ce :out std_logic
);end component;
component counter60
port(
clk1hz :in std_logic;
en :in std_logic;
enout :out std_logic;
low :out std_logic_vector(3 downto 0);
high :out std_logic_vector(3 downto 0)
);end component;
component counter24
port(
in_date :in std_logic_vector(3 downto 0);
out_date :out std_logic_vector(6 downto 0)
);end component;
component display
port(
clk1hz :in std_logic;
en :in std_logic;
enout :out std_logic;
low :out std_logic_vector(3 downto 0);
high :out std_logic_vector(3 downto 0)
);end component;
constant vcc :std_logic :='1';
signal vcc_con :std_logic;
signal s_enout :std_logic;
signal m_enout :std_logic;
signal clk :std_logic;
signal s_ce :std_logic;
signal m_ce :std_logic;
signal h_ce :std_logic;
signal sl :std_logic_vector(3 downto 0);
signal sh :std_logic_vector(3 downto 0);
signal ml :std_logic_vector(3 downto 0);
signal mh :std_logic_vector(3 downto 0);
signal hl :std_logic_vector(3 downto 0);
signal hh :std_logic_vector(3 downto 0);
begin
adjust_control :adjuster
port map(
clk1hz =>clk1hz,
set =>set,
mode =>mode,
en =>vcc_com,
s_enout=>s_enout,
m_enout=>m_enout,
clk =>clk,
s_ce =>s_ce,
m_ce =>m_ce,
h_ce =>h_ce
);vcc_con <= vcc;
sec_control:counter60
port map(
clk1hz =>clk,
en =>s_ce,
enout =>s_enout,
low =>sl,
high =>sh
);min_control :counter60
port map(
clk1hz =>clk,
en =>m_ce,
enout =>m_enout,
low =>ml,
high =>mh
);hour_control :counter24
port map(
clk1hz =>clk,
en =>h_ce,
low =>hl,
high =>hh
);dis_led1 :display
port map(
in_date =>sl,
out_date =>led1
);dis_led2 :display
port map(
in_date =>sh,
out_date =>led2
);dis_led3 :display
port map(
in_date =>ml,
out_date =>led3
);dis_led4 :display
port map(
in_date =>mh,
out_date =>led4
);dis_led5 :display
port map(
in_date =>hl,
out_date =>led5
);dis_led6 :display
port map(
in_date =>hh,
out_date =>led6
);end rtl;
60進製計數模組
--counter60.vhd
----
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter60 is
port(
clk1hz :in std_logic;
en :in std_logic;
enout :out std_logic;
low :out std_logic_vector(3 downto 0);
high :out std_logic_vector(3 downto 0)
);end counter60;
architecture rtl of counter60 is
signal low_reg :std_logic_vector(3 downto 0) :="0000";
signal high_reg :std_logic_vector(3 downto 0) :="0000";
begin
low_proc :process(clk1hz,en)
begin
if rising_edge(clk1hz) then
if en='1' then
if low_reg="1001" then
low_reg<="0000";
else
low_reg<=low_reg + '1';
end if;
end if;
end if;
end process;
low<=low_reg;
high_proc :process(clk1hz,en)
begin
if rising_edge(clk1hz) then
if en='1' then
if low_reg="1001" then
if high_reg="0101" then
high_reg<="0000";
else
high_reg<=high_reg + '1';
enf if;
end if;
end if;
end if;
end process;
high<=high_reg;
enout<='1' when low_reg="1001" and high_reg="0101" else '0';
end rtl;
24進製bcd碼計數模組
--counter24.vhd
----
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter24 is
port(
clk1hz :in std_logic;
en :in std_logic;
enout :out std_logic;
low :out std_logic_vector(3 downto 0);
high :out std_logic_vector(3 downto 0)
);end counter24;
architecture rtl of counter24 is
signal low_reg :std_logic_vector(3 downto 0) :="0000";
signal high_reg :std_logic_vector(3 downto 0) :="0000";
signal clr :std_logic :='0';
begin
low_proc :process(clk1hz,en,clr)
begin
if rising_edge(clk1hz) then
if en='1' then
if low_reg="1001" or clr='1' then
low_reg<="0000";
else
low_reg<=low_reg + '1';
end if;
end if;
end if;
end process;
low<=low_reg;
high_proc :process(clk1hz,en)
begin
if rising_edge(clk1hz) then
if en='1' then
if clr='1' then
high_reg<="0000";
elseif low_reg="1001" then
high_reg<=high_reg + '1';
end if;
end if;
end if;
end process;
high<=high_reg;
clr<='1' when low_reg="0011" and high_reg="0010" else '0';
end rtl;
校正模組
--adjuster.vhd
----
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity adjuster is
port(
clk1hz :in std_logic;
set :in std_logic;
node :in std_logic;
en :in std_logic;
s_enout :in std_logic;
m_enout :in std_logic;
clk :out std_logic;
s_ce :out std_logic;
m_ce :out std_logic;
h_ce :out std_logic
);end adjuster;
architecture rtl of adjuster is
signal sel :std_logic;
signal sce_reg :std_logic;
signal mce_reg :std_logic;
signal hce)reg :std_logic;
signal con :integer range 0 to 3 := 0;
begin
cout:process(mode,set)
begin
if rising_edg(mode) then
if con = 3 rhen
con<=0;
else
con<=con +1;
end if;
end if;
end process;
con_pro:process(con)
begin
case con is
when 0=>sel<='1';
sce_reg<='0';
mce_reg<='0';
hce_reg<='0';
when 1=>sel<='0';
sce_reg<='1';
mce_reg<='0';
hce_reg<='0';
when 2=>sel<='0';
sce_reg<='0';
mce_reg<='1';
hce_reg<='0';
when 3=>sel<='0';
sce_reg<='0';
mce_reg<='0';
hce_reg<='1';
when others =>sel<='0';
sce_reg<='0';
mce_reg<='0';
hce_reg<='0';
end case;
end process;
sel_pro:process(sel)
begin
case sel is
when 0=>s_ce<=sce_reg;
m_ce<=mce_reg;
h_ce<=hce_reg';
clk<=set;
when 0=>s_ce<=en;
m_ce<=s_enout;
h_ce<=m_enout';
clk<=clk1hz;
when others =>s_ce<=en;
m_ce<=s_enout;
h_ce<=m_enout';
clk<=clk1hz;
end case;
end process;
end rtl;
顯示模組
--display.vhd
----
library ieee
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity display is
prot(
in_date :in std_logic_vector(3 downto 0);
out_date :out std_logic_vector(6 downto 0)
);end display;
architecture rtl of display is
begin
case in_dateis
when "0000"=>out_date<="0111111";
when "0001"=>out_date<="0000110";
when "0010"=>out_date<="1011011";
when "0011"=>out_date<="1001111";
when "0100"=>out_date<="1100110";
when "0101"=>out_date<="1101101";
when "0110"=>out_date<="1111100";
when "0111"=>out_date<="0000111";
when "1000"=>out_date<="1111111";
when "1001"=>out_date<="1100111";
when others =>out_date<="0000000";
end case;
end process;
end rtl;
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